With the SIPLACE CA, you can integrate fast-growing future technologies such as flip chip (FC) and die attach (DA) into your SMT production. The SIPLACE CA is the first high-speed placement platform that lets you flexibly combine bare-die placement directly from the wafer with conventional feeder-based SMT placement. Your competitive advantage: new, future-oriented applications can be implemented on a single SMT line without any additional special processes. It is the ideal machine for “advanced packaging” applications. Another benefit: for all other jobs, the SIPLACE CA serves as a powerful “regular” SMT placement machine.
For Flip Chip (FC) and Die Attach (DA) Placement
- 4 SIPLACE CP20 placement heads support high-accuracy placement of up to 126,000 SMT components, 46,000 flip chips or 30,000 bare dies per hour
- Component supply from feeder trolleys or feeders, or 4-12 inch wafers via the SIPLACE Wafer System (SIPLACE SWS)
- Die attach and linear dipping module
- High-accuracy bare-die placement, supporting embedded wafer-level ball grid array (eWLB)
- Placement accuracy up to 10 µm @ 3 s
- Handles boards up to 850 mm x 560 mm (long-board option, standard single lane)
- Only 2 meters long (20% shorter than before)
- Can be equipped with the SIPLACE CPP placement head
- Minimized placement force, as low as 0.5 N
- Linear dipping module with vision inspection and automatic flux thickness adjustment
SIPLACE CA Dual Lane
T&R 126,500 components / hour
Wafer 46,000 components / hour
Up to 160 x 8 mm feeder tracks or 4 wafer feeders
SIPLACE CA Wafer Lane
T&R 126,500 components / hour
Wafer 46,000 components / hour
Up to 160 x 8 mm feeder tracks or 4 wafer feeders
SIPLACE CA Panel Lane
T&R 126,500 components / hour
Wafer 46,000 components / hour
Up to 160 x 8 mm feeder tracks or 4 wafer feeders
3 conveyor versions, configurable to your needs
- Dual Lane conveyor for Standard SiP and Module.
- Wafer Lane conveyor for Wafer fan-out, Wafer SiP and Chip on Wafer processes
- Panel Lane conveyor for Panel fan-out and Embedded Die processes with substrates up to 685 x 685 mm
Specifications
| SIPLACE CA | Panel Level Configuration | Wafer Level Configuration | ||||
|---|---|---|---|---|---|---|
| Application | Flip Chip | Die Attach | Flip Chip | Die Attach | SMD | |
| Accuracy | ± 12 µm at 3 σ | ± 12 µm at 3 σ | ± 10 µm at 3 σ | ± 10 µm at 3 σ | ± 15 µm at 3 σ | |
| Throughput (flip chip without dipping) | CP20M2 | 46 | 30 | 46 | 30 | 126.000 |
| CPPM | 41 | 29 | 41 | 29 | 85.000 | |
| Die / component sizes CP20M2 | 0.5 – 6mm | 0.8 – 6 mm | 0.5 – 6mm | 0.8 – 6 mm | 0201m – 6mm | |
| Die / component sizes CPPM | 0.5 – 15mm | 0.8 – 15mm | 0.5 – 15mm | 0.8 – 15mm | 0402m – 15mm | |
| Die thickness min. (Silicon) | 50 µm | 50 µm | 50 µm | 50 µm | n / a | |
| Bump size min. 3) | 25 µm | n / a | 25 µm | n / a | n / a | |
| Bump pitch min. 3) | 50 µm | n / a | 50 µm | n / a | n / a | |
| SIPLACE Wafer System SWS | Horizontal system, automatic wafer exchange, MCM | |||||
| SWS wafer size | 4″ – 12″ | n / a | ||||
| Wafer stretcher | 12″ / 8″ | n / a | ||||
| Wafer stretch range | 2mm – 8 mm | n / a | ||||
| Die eject system | Programmable eject speed | |||||
| Linear Dipping Unit LDU | Free programmable flux application speed |